| General information | |
|---|---|
| Launched | November 4, 2021[1] |
| Designed by | Intel |
| Common manufacturer(s) | |
| Cache | |
| L1 cache | 80 KB per core (32 KB instructions + 48 data) |
| L2 cache | 1.25 MB per core (client)2 MB per core (server) |
| L3 cache | 3 MB per core |
| Architecture and classification | |
| Technology node | Intel 7 (previously known as 10ESF) |
| Instruction set | x86-64 |
| Extensions | |
| Products, models, variants | |
| Product code name(s) |
|
| History | |
| Predecessor | Sunny Cove (1S and 2S servers, 10 nm) Skylake (4S and 8S servers, 14 nm) Willow Cove (mobile, 10 nm) Cypress Cove (desktop, 14 nm) |
Golden Cove is a codename for a CPU microarchitecture developed by Intel and released in November, 2021. It succeeds four microarchitectures: Sunny Cove, Skylake, Willow Cove, and Cypress Cove.[2][3][4] It is fabricated using Intel's 7 nm class process node called Intel 7, previously referred to as 10 nm Enhanced SuperFin (10ESF).
The microarchitecture is used in the high-performance cores (P-core) of the 12th-generation Intel Core processors (codenamed "Alder Lake") and will power 4th-generation Xeon Scalable server processors (codenamed "Sapphire Rapids").[4][5]
Features[edit]
Intel first unveiled Golden Cove during their Architecture Day 2020.[6] Further details were released by Intel in August 2021, during their next Architecture Day.[7]
Similar to Skylake, Golden Cove is a major update to the core microarchitecture, with Intel stating that will "allow performance for the next decade of compute". Intel considers Golden Cove to be the largest microarchitectural upgrade to the Core family in a decade. Intel touts a 19% IPC increase over Cypress Cove.[7]
Improvements[edit]
- New 6-wide instruction decoder (up from 4-wide in previous microarchitectures) with the ability to fetch up to 32 bytes of instructions per cycle (up from 16)[7]
- Wider 6-wide microarchitecture
- µOP cache size increased to 4K entries (up from 2.25K)
- 12 execution ports (up from 10)[7]
- Larger out-of-order instruction window compared to Sunny Cove, with the re-order buffer (ROB) size increased from 352 to 512 entries
- Larger Vector/FP Register File, which was increased from 224 to 332 entries[8]
- Larger Load and Store queues (192 and 114 respectively, from 128 and 72 in Sunny Cove)[8]
- Larger L2 cache for server variants (2 MB per core from 1.25 MB per core)
- New instruction set extensions:[9]
- CLDEMOTE
- PTWRITE
- User Wait: TPAUSE, UMONITOR, UMWAIT
- Architectural LBRs
- Hypervisor-managed Linear Address Translation (HLAT)
- SERIALIZE
- Enhanced Hardware Feedback Interface (EHFI) and HRESET
- AVX-VNNI
- AVX-512 with AVX512-FP16
- In server Sapphire Rapids CPUs:
Products[edit]
The microarchitecture is used in the high-performance cores of the twelfth generation of Intel Core hybrid processors (codenamed "Alder Lake") and will be implemented in the fourth generation of Xeon scalable processors (codenamed "Sapphire Rapids").
See also[edit]
References[edit]
- ^ Cutress, Dr. Ian. "Intel 12th Gen Core Alder Lake for Desktops: Top SKUs Only, Coming November 4th". www.anandtech.com.
- ^ Dexter, Alan (2021-04-06). "Intel Alder Lake CPUs: What are they, when will they launch, and how fast will they be?". PC Gamer. Retrieved 2021-04-07.
- ^ Mujtaba, Hassan (2019-05-21). "Intel Xeon Roadmap Leak, 10nm Ice Lake, Sapphire Rapids CPU Detailed". Wccftech. Retrieved 2020-03-14.
- ^ a b "Intel: Alder Lake Sampling, Sapphire Rapids Samples in Q4". Tom's Hardware.
- ^ Pirzada, Usman (2020-10-07). "Intel Sapphire Rapids: MCM Design, 56 Golden Cove Cores, 64GB HBM2 On-Board Memory, Massive IPC Improvement and 400 Watt TDP". Wccftech. Retrieved 2021-04-06.
- ^ Cutress, Dr Ian. "Intel Alder Lake: Confirmed x86 Hybrid with Golden Cove and Gracemont for 2021". www.anandtech.com. Retrieved 2021-02-15.
- ^ a b c d Cutress, Dr Ian; Frumusanu, Andrei. "Intel Architecture Day 2021: Alder Lake, Golden Cove, and Gracemont Detailed". www.anandtech.com. Retrieved 2021-08-21.
- ^ a b "Popping the Hood on Golden Cove". Chips and Cheese. 2021-12-02. Retrieved 2021-12-28.
- ^ https://software.intel.com/content/dam/develop/external/us/en/documents-tps/architecture-instruction-set-extensions-programming-reference.pdf