In computer engineering, a load–store architecture (or a register–register architecture) is an instruction set architecture that divides instructions into two categories: memory access (load and store between memory and registers) and ALU operations (which only occur between registers).[1]: 9–12
Some RISC architectures such as PowerPC, SPARC, RISC-V, ARM, and MIPS are load–store architectures.[1]: 9–12
For instance, in a load–store approach both operands and destination for an ADD operation must be in registers. This differs from a register–memory architecture (for example, a CISC instruction set architecture such as x86) in which one of the operands for the ADD operation may be in memory, while the other is in a register.[1]: 9–12
The earliest example of a load–store architecture was the CDC 6600.[1]: 54–56 Almost all vector processors (including many GPUs[2][better source needed]) use the load–store approach.[3]
See also
[edit]References
[edit]- ^ a b c d Michael J. Flynn (1995). Computer architecture: pipelined and parallel processor design. ISBN 0867202041.
- ^ "AMD GCN reference" (PDF).
- ^ Harvey G. Cragon (1996). Memory systems and pipelined processors. pp. 512–513. ISBN 0867204745.
Well, that’s interesting to know that Psilotum nudum are known as whisk ferns. Psilotum nudum is the commoner species of the two. While the P. flaccidum is a rare species and is found in the tropical islands. Both the species are usually epiphytic in habit and grow upon tree ferns. These species may also be terrestrial and grow in humus or in the crevices of the rocks.
View the detailed Guide of Psilotum nudum: Detailed Study Of Psilotum Nudum (Whisk Fern), Classification, Anatomy, Reproduction