| General information | |
|---|---|
| Launched | 2019-08-29[1] |
| Designed by | IBM, OpenPOWER Foundation |
| Architecture and classification | |
| Application | Soft core |
| Instruction set | Power ISA 3.0 ppc64le ppc64be |
| Physical specifications | |
| Cores |
|
Microwatt is an open source soft processor core originally written in VHDL by Anton Blanchard at IBM, announced at the OpenPOWER Summit NA 2019[2] and published on GitHub in August 2019. It adheres to the Power ISA 3.0 instruction set and can be run on FPGA boards, booting Linux, MicroPython and Zephyr.[3][4][5][6][7][8]
Design[edit]
Microwatt is a tiny 64-bit bi-endian scalar integer processor core, implementing a subset of the Power ISA 3.0 instruction set. It has 32× 64-bit general purpose registers and 32x 64-bit floating-point registers. It uses Wishbone for the memory interface.[4]
The initial development was done in a couple of months, included the entire integer processing functionality of the instruction set; the bare minimum to make it compliant, with no memory management unit (MMU) and no floating-point unit.[4]
Later additions to the implementation includes JTAG debugger interface, divider instructions, 16 KB instruction and 32 KB data caches, a non-hypervisor-capable MMU, pipelining[4] and floating-point support.[9]
It's designed using VHDL 2008 and the GHDL simulation environment.[3]
Chiselwatt[edit]
A sibling project called Chiselwatt is another open processor core implementing the Power ISA 3.0 instruction set, written in the Scala-based Chisel instead of VHDL.[10][11]
Implementations[edit]
- Microwatt itself
- Libre-SOC – A libre system on a chip under development that uses Microwatt as a reference design.[12]
- Kestrel – A soft BMC in Raptor Engineering POWER9 based workstations.[13][14]
History[edit]
It is the first processor written from scratch using the open Power ISA 3.0, and is released by the OpenPOWER Foundation as a reference design.
The project started as a demo, proof of concept and a reference implementation for the release of the opensource initiative regarding Power ISA 3.0.[15] The goal for Blanchard was to see if he could make it, and as a software developer, taking on a very low level hardware project was a challenge.[2][3]
Microwatt is set to be fabricated in 130 nm by Efabless "Open MPW Shuttle Program" in 2021.[16] As of February 2024, there has been no update on the progress of fabrication on Efabless's Microwatt project page.[17]
See also[edit]
References[edit]
- ^ Williams, Chris (2019-08-29). "Get your royalty-free soft-core OpenPOWER processor core blueprints here. Extra, extra – read all about it". The Register.
- ^ a b OpenPOWER Summit NA 2019: Day 2 Keynote Demonstration: Anton Blanchard, IBM & Joe DeLaere, Xilinx
- ^ a b c "POWER OpenISA and Microwatt introduction" - Anton Blanchard (LCA 2020)
- ^ a b c d "Microwatt Microarchitecture" - Paul Mackerras (LCA 2020)
- ^ Microwatt and the POWER ISA support in Renode
- ^ Linux on Microwatt
- ^ OpenPOWER opens further
- ^ Day 2 keynote and OpenPOWER blows the doors off: Royalty-free, open soft-core (RISC-V sweating gallons)
- ^ Microwatt Floats
- ^ Chiselwatt's page on Github
- ^ Final Draft of the Power ISA EULA Released
- ^ Libre-SOC
- ^ "Raptor Announces Kestrel Open-Source, Open HDL/Firmware Soft BMC".
- ^ Kestrel SoftBMC Project
- ^ Big Blue open sources POWER chip instruction set
- ^ "Open MPW metadata for Microwatt". Archived from the original on 2021-02-28. Retrieved 2021-03-30.
- ^ "Efabless". Efabless. Retrieved 2024-02-16.