Semiconductor device fabrication
MOSFET scaling (process nodes)
020 µm – 1968 010 µm – 1971 006 µm – 1974 003 µm – 1977  1.5 µm – 1981 001 µm – 1984 800 nm – 1987 600 nm – 1990 350 nm – 1993 250 nm – 1996 180 nm – 1999 130 nm – 2001 090 nm – 2003 065 nm – 2005 045 nm – 2007 032 nm – 2009 028 nm – 2010 022 nm – 2012 014 nm – 2014 010 nm – 2016 007 nm – 2018 005 nm – 2020 003 nm – 2022
Future 002 nm ~ 2024
Half-nodes Density CMOS Device (multi-gate) Moore's law Transistor count Semiconductor Industry Nanoelectronics

The "22 nm" node is the process step following 32 nm in CMOS MOSFET semiconductor device fabrication. The typical half-pitch (i.e., half the distance between identical features in an array) for a memory cell using the process is around 22 nm.^{[citation needed]} It was first demonstrated by semiconductor companies for use in RAM memory in 2008. In 2010, Toshiba began shipping 24 nm flash memory chips, and Samsung Electronics began mass-producing 20 nm flash memory chips. The first consumer-level CPU deliveries using a 22 nm process started in April 2012 with the Intel Ivy Bridge processors.

Since at least 1997, "process nodes" have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit;^[1] neither gate length, metal pitch or gate pitch on a "22nm" device is twenty-two nanometers.^[2][3][4][5]

The ITRS 2006 Front End Process Update indicates that equivalent physical oxide thickness will not scale below 0.5 nm (about twice the diameter of a silicon atom), which is the expected value at the 22 nm node. This is an indication that CMOS scaling in this area has reached a wall at this point, possibly disturbing Moore's law.

The 20-nanometre node is an intermediate half-node die shrink based on the 22-nanometre process.

TSMC began mass production of 20 nm nodes in 2014.^[6] The 22 nm process was superseded by commercial 14 nm FinFET technology in 2014.

Technology demos[edit]

On August 18, 2008, AMD, Freescale, IBM, STMicroelectronics, Toshiba, and the College of Nanoscale Science and Engineering (CNSE) announced that they jointly developed and manufactured a 22 nm SRAM cell, built on a traditional six-transistor design on a 300 mm wafer, which had a memory cell size of just 0.1 μm².^[7] The cell was printed using immersion lithography.^[8]

The 22 nm node may be the first time where the gate length is not necessarily smaller than the technology node designation. For example, a 25 nm gate length would be typical for the 22 nm node.

On September 22, 2009, during the Intel Developer Forum Fall 2009, Intel showed a 22 nm wafer and announced that chips with 22 nm technology would be available in the second half of 2011.^[9] SRAM cell size is said to be 0.092 μm², smallest reported to date.

On January 3, 2010, Intel and Micron Technology announced the first in a family of 25 nm NAND devices.

On May 2, 2011, Intel announced its first 22 nm microprocessor, codenamed Ivy Bridge, using a FinFET technology called 3-D tri-gate.^[10]

IBM's POWER8 processors are produced in a 22 nm SOI process.^[11]

Shipped devices[edit]

• Toshiba announced that it was shipping 24 nm flash memory NAND devices on August 31, 2010.^[12]
• In 2010, Samsung Electronics began mass production of 64 Gbit NAND flash memory chips using a 20 nm process.^[13]
• Also in 2010, Hynix introduced a 64 Gbit NAND flash memory chip using a 20 nm process.^[14]
• On April 23, 2012, Intel Core i7 and Intel Core i5 processors based on Intel's Ivy Bridge 22 nm technology for series 7 chipsets went on sale worldwide.^[15] Volume production of 22 nm processors began more than six months earlier, as confirmed by former Intel CEO Paul Otellini on October 19, 2011.^[16]
• On June 3, 2013, Intel started shipping Intel Core i7 and Intel Core i5 processors based on Intel's Haswell microarchitecture in 22 nm tri-gate FinFET technology for series 8 chipsets.^[17] Intel's 22nm process has a transistor density of 16.5 million transistors per square milimeter (MTr/mm2).^[18]

References[edit]