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	This article appeared on Wikipedia's Main Page as Today's featured article on January 7, 2005.
Article milestones Date Process Result September 15, 2004 Featured article candidate Promoted July 11, 2007 Featured article review Demoted
Current status: Former featured article

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There was an apparent merger with the L1, L2, and L3 caches of a CPU. I would like it if there were sections depicting each or at least a section that explains them. — Preceding unsigned comment added by Laboye (talk • contribs) 14:49, 20 September 2006‎ (UTC)[reply]

I find it confusing that the same word (index) denotes both tags in the Tag SRAM and words in the Data SRAM. Index often denotes the part of address used for selecting the whole cache line (Addr[10:6]), which is not the same as the part used for addressing the Data SRAM (Addr[10:2]) as shown in the image.

Usually people draw the index field connected to a decoder which selects the line. The relevant portion of the line is finally extracted by an additional decoder, which is addressed by the offset field of the address.

The detached organization in the image is also fine, but the words "index" in each line seem redundand and confusing.

Perhaps you could attribute Data SRAM entries as word 0, word 1, etc, and the Tag SRAM entries as tag 0, tag 1, etc? — Preceding unsigned comment added by 161.53.65.130 (talk • contribs) 10:47, 17 November 2008‎ (UTC

A scratchpad memory is working memory for a component of a computing system, and is not a cache or similar to a cache in its role. Shmuel (Seymour J.) Metz Username:Chatul (talk) 01:07, 25 February 2021 (UTC)[reply]

• L0 - on slides of AMD's RDNA3 architecture
• K cache - on slides of AMD's RDNA3 architecture
• RB cache- on slides of AMD's RDNA3 architecture
• Write cache [1]

37.205.108.123 (talk) 14:09, 24 March 2024 (UTC)[reply]

• 3D cache / stacked cache [2]
• V-Cache [3] — Preceding unsigned comment added by Setenzatsu.2 (talk • contribs) 17:50, 25 March 2024 (UTC)[reply]

Are "3D caches"/"stacked caches"/"vertical caches"/etc. just different packaging/interconnects for CPU caches? Guy Harris (talk) 18:15, 25 March 2024 (UTC)[reply]