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| title = [[Central processing unit|CPU technologies]]
| title = [[Central processing unit|CPU technologies]]


| group1 = [[Instruction set architecture|Architecture]]
|group1 = [[Instruction set architecture|Architecture]]
| list1 = [[Instruction set|Instruction Set Architecture]]{{·}} [[Reduced instruction set computer|RISC]]{{·}} [[Complex instruction set computer|CISC]]{{·}} [[Explicitly parallel instruction computing|EPIC]]{{·}} [[Very long instruction word|VLIW]]{{·}} [[One instruction set computer|OISC]]{{·}} [[Zero Instruction Set Computer|ZISC]]{{·}} [[Harvard architecture]]{{·}} [[Von Neumann architecture]]
|list1 = [[Instruction set|Instruction Set Architecture]]{{·}} [[Complex instruction set computer|CISC]]
{{·}} [[Explicitly parallel instruction computing|EPIC]]{{·}} [[One instruction set computer|OISC]]{{·}}[[Reduced instruction set computer|RISC]]{{·}} [[Very long instruction word|VLIW]]{{·}} [[Zero Instruction Set Computer|ZISC]]{{·}} [[Complex instruction set computer#CISC_and_RISC_processors|CISC-RISC (x86)]]{{·}} [[Harvard architecture]]{{·}} [[Von Neumann architecture]]{{·}} [[Bitwise operation]]
| group2 = [[Parallel computing|Parallelism]]
|group2 = [[Parallel computing|Parallelism]]
| list2 = [[Instruction pipeline|Instruction pipelining]]{{·}} [[Superscalar]]{{·}} [[Out-of-order execution]]{{·}} [[Register renaming]]{{·}} [[Speculative execution]]{{·}} [[Multithreading (computer hardware)|Multithreading]]{{·}} [[Multiprocessing]]
|list2 = [[Instruction pipeline|Instruction pipelining]]{{·}} [[Superscalar]]{{·}} [[Out-of-order execution]]{{·}} [[Register renaming]]{{·}} [[Speculative execution]]{{·}} [[Multithreading (computer hardware)|Multithreading]]{{·}} [[Multiprocessing]]
| group3 = Components
|group3 = Components
| list3 = [[Arithmetic logic unit|ALU]]{{·}} [[Floating point unit|FPU]]{{·}} [[Vector processor]]{{·}} [[SIMD]]{{·}} [[32-bit]]/[[64-bit]]{{·}} [[Processor register|Registers]]{{·}} [[CPU cache|Cache]]{{·}} [[Application-specific integrated circuit|ASIC]]{{·}} [[Field-programmable gate array|FPGA]]{{·}} [[Digital signal processor|DSP]]{{·}} [[Microcontroller]]{{·}} [[Application-specific instruction-set processor|ASIP]]{{·}} [[System-on-a-chip|SoC]]
|list3 = [[Arithmetic logic unit|ALU]]{{·}} [[Floating point unit|FPU]]{{·}} [[Vector processor]]{{·}} [[SIMD]]{{·}} [[32-bit]]/[[64-bit]]{{·}} [[Processor register|Registers]]{{·}} [[CPU cache|Cache]]{{·}} [[Application-specific integrated circuit|ASIC]]{{·}} [[Field-programmable gate array|FPGA]]{{·}} [[Digital signal processor|DSP]]{{·}} [[Microcontroller]]{{·}} [[Application-specific instruction-set processor|ASIP]]{{·}} [[System-on-a-chip|SoC]]
| group4 = [[Power management]]
|group4 = [[Power management]]
| list4 = [[Dynamic frequency scaling]]{{·}} [[Dynamic voltage scaling]]{{·}} [[Clock gating]]
|list4 = [[Dynamic frequency scaling]]{{·}} [[Dynamic voltage scaling]]{{·}} [[Clock gating]]
}}<noinclude>
}}<noinclude>


Revision as of 19:35, 1 September 2008

source: https://en.wikipedia.org/w/index.php?title=Template:CPU_technologies&diff=next&oldid=233464268